Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, scalable superconducting memory still poses a challenge. To address this issue, we present an alternative to approaches that solely emphasize storage cell miniaturization by exploiting the minimal attenuation and dispersion properties of superconducting passive transmission lines to develop a delay-line memory system. This fully superconducting design operates at speeds between 20 GHz and 100 GHz, with $\pm$24\% and $\pm$13\% bias margins, respectively, and demonstrates data densities in the 10s of Mbit/cm$^2$ with the MIT Lincoln Laboratory SC2 fabrication process. Additionally, the circulating nature of this design allows for minimal control circuitry, eliminates the need for data splitting and merging, and enables inexpensive implementations of sequential access and content-addressable memories. Further advances in fabrication processes suggest data densities of 100s of Mbit/cm$^2$ and beyond

翻译：近期逻辑方案与制造工艺的进展重新激发了超导电子学在节能计算和量子控制处理器中的应用兴趣。然而，可扩展的超导存储仍构成挑战。为解决此问题，我们提出了一种替代仅强调存储单元微型化的方法，通过利用超导无源传输线的最小衰减和色散特性，开发延迟线存储系统。这种全超导设计在20 GHz至100 GHz速度范围内运行，分别具有±24%和±13%的偏置容限，并通过MIT林肯实验室SC2制造工艺展示了数十Mbit/cm²的数据密度。此外，该设计的循环特性使得控制电路最少化，无需数据拆分与合并，并支持低成本实现顺序访问和内容可寻址存储器。制造工艺的进一步进步预示着数据密度可达数百Mbit/cm²及以上。