Our ISCA 2013 paper provides a fundamental empirical understanding of two major factors that make it very difficult to determine the minimum data retention time of a DRAM cell, based on the first comprehensive experimental characterization of retention time behavior of a large number of modern commodity DRAM chips from 5 major vendors. We study the prevalence, effects, and technology scaling characteristics of two significant phenomena: 1) data pattern dependence (DPD), where the minimum retention time of a DRAM cell is affected by data stored in other DRAM cells, and 2) variable retention time (VRT), where the minimum retention time of a DRAM cell changes unpredictably over time. To this end, we built a flexible FPGA-based testing infrastructure to test DRAM chips, which has enabled a large amount of further experimental research in DRAM. Our ISCA 2013 paper's results using this infrastructure clearly demonstrate that DPD and VRT phenomena are significant issues that must be addressed for correct operation in DRAM-based systems and their effects are getting worse as DRAM scales to smaller technology node sizes. Our work also provides ideas on how to accurately identify data retention times in the presence of DPD and VRT, e.g., online profiling with error correcting codes, which later works examined and enabled. Most modern DRAM chips now incorporate ECC, especially to account for VRT effects. This short retrospective provides a brief analysis of our ISCA 2013 paper and its impact. We describe why we did the work, what we found and its implications, what the findings as well as the infrastructure we built to discover them have enabled in later works, and our thoughts on what the future may bring.

翻译：我们在ISCA 2013发表的论文，通过对来自5大主流厂商的大量现代商用DRAM芯片进行首次全面的数据保持时间行为实验表征，为理解导致确定DRAM单元最小数据保持时间极为困难的两个主要因素提供了基础性实证认知。我们研究了两种重要现象的普遍性、影响及技术缩放特性：1）数据模式依赖性（DPD），即DRAM单元的最小保持时间受其他DRAM单元存储数据的影响；2）可变保持时间（VRT），即DRAM单元的最小保持时间随时间不可预测地变化。为此，我们构建了基于FPGA的灵活测试基础设施以测试DRAM芯片，该设施为后续大量DRAM实验研究奠定了基础。基于该基础设施的ISCA 2013论文结果清晰表明，DPD和VRT现象是DRAM系统正常运行时必须解决的关键问题，且随着DRAM工艺节点尺寸缩小，其影响日益恶化。我们的工作还提出了在DPD和VRT存在时如何准确识别数据保持时间的思路（例如利用纠错码进行在线分析），后续研究对此进行了探讨并付诸实践。如今多数现代DRAM芯片已集成ECC（纠错码），尤其为应对VRT效应。本简要回顾系统分析了我们ISCA 2013论文及其影响，阐述了研究动机、核心发现及其启示，分析了研究成果及构建的实验基础设施对后续工作的推动作用，并对未来发展方向提出了展望。