Computing-in-Memory (CIM) architectures have emerged as a promising solution for accelerating Deep Neural Networks (DNNs) by mitigating data movement bottlenecks. However, realizing the potential of CIM requires specialized dataflow optimizations, which are challenged by an expansive design space and strict architectural constraints. Existing optimization approaches often fail to fully exploit CIM accelerators, leading to noticeable gaps between theoretical and actual system-level efficiency. To address these limitations, we propose the MIREDO framework, which formulates dataflow optimization as a Mixed-Integer Programming (MIP) problem. MIREDO introduces a hierarchical hardware abstraction coupled with an analytical latency model designed to accurately reflect the complex data transfer behaviors within CIM systems. By jointly modeling workload characteristics, dataflow strategies, and CIM-specific constraints, MIREDO systematically navigates the vast design space to determine the optimal dataflow configurations. Evaluation results demonstrate that MIREDO significantly enhances performance, achieving up to $3.2\times$ improvement across various DNN models and hardware setups.

翻译：存内计算（CIM）架构通过缓解数据移动瓶颈，已成为加速深度神经网络（DNN）的一种有前景的解决方案。然而，实现CIM的潜力需要专门的数据流优化，这面临着广阔的设计空间和严格的架构约束的挑战。现有优化方法往往无法充分利用CIM加速器，导致理论效率与实际系统级效率之间存在显著差距。为解决这些局限性，我们提出了MIREDO框架，该框架将数据流优化表述为一个混合整数规划（MIP）问题。MIREDO引入了一种层次化的硬件抽象，并结合了一个旨在准确反映CIM系统内复杂数据传输行为的分析性延迟模型。通过联合建模工作负载特性、数据流策略以及CIM特定的约束，MIREDO系统地探索广阔的设计空间，以确定最优的数据流配置。评估结果表明，MIREDO显著提升了性能，在各种DNN模型和硬件设置下实现了高达$3.2\times$的性能提升。