This paper presents a low-latency hardware accelerator for modular polynomial multiplication for lattice-based post-quantum cryptography and homomorphic encryption applications. The proposed novel modular polynomial multiplier exploits the fast finite impulse response (FIR) filter architecture to reduce the computational complexity of the schoolbook modular polynomial multiplication. We also extend this structure to fast $M$-parallel architectures while achieving low-latency, high-speed, and full hardware utilization. We comprehensively evaluate the performance of the proposed architectures under various polynomial settings as well as in the Saber scheme for post-quantum cryptography as a case study. The experimental results show that our proposed modular polynomial multiplier reduces the computation time and area-time product, respectively, compared to the state-of-the-art designs.

翻译：本文提出了一种用于格基后量子密码和同态加密应用中模多项式乘法的低延迟硬件加速器。所提出的新型模多项式乘法器利用快速有限冲激响应(FIR)滤波器架构，降低了教科书式模多项式乘法的计算复杂度。我们还将该结构扩展到快速$M$并行架构，同时实现了低延迟、高速度和完全硬件利用率。我们全面评估了所提架构在不同多项式设置下的性能，并以Saber方案作为后量子密码的案例研究。实验结果表明，与现有最优设计相比，我们提出的模多项式乘法器在计算时间和面积-时间乘积上均有显著降低。