The outsourced manufacturing of integrated circuits has increased the risk of intellectual property theft. In response, logic locking techniques have been developed for protecting designs by adding programmable elements to the circuit. These techniques differ significantly in both overhead and resistance to various attacks, leaving designers unable to discern their efficacy. To overcome this critical impediment for the adoption of logic locking, we propose two metrics, key corruption and minimum corruption, that capture the goals of locking under different attack scenarios. We develop a flow for approximating these metrics on generic locked circuits and evaluate several locking techniques.

翻译：外包的集成电路制造增加了知识产权盗窃的风险,作为回应,为保护设计开发了逻辑锁定技术,在电路中添加了可编程元素,这些技术在间接费用和抵抗各种袭击方面差异很大,使得设计师无法辨别其功效。为了克服这一使用逻辑锁定的关键障碍,我们建议采用两种衡量标准,即关键腐败和最低限度腐败,以捕捉不同攻击情景下锁定目标。我们开发了一种对通用锁定电路进行近似这些测量的流程,并评估了几种锁定技术。