Spin Transfer Torque Random Access Memory (STT-RAM) is an emerging Non-Volatile Memory (NVM) technology that has garnered attention to overcome the drawbacks of conventional CMOS-based technologies. However, such technologies must be evaluated before deployment under real workloads and architecture. But there is a lack of available open-source STT-RAM-based system evaluation framework, which hampers research and experimentation and impacts the adoption of STT- RAM in a system. This paper proposes a novel, extendable STT-RAM memory controller design integrated inside the gem5 simulator. Our framework enables understanding various aspects of STT-RAM, i.e., power, delay, clock cycles, energy, and system throughput. We will open-source our HOPE framework, which will fuel research and aid in accelerating the development of future system architectures based on STT-RAM. It will also facilitate the user for further tool enhancement.

翻译：自旋转移矩随机访问存储器（STT-RAM）是一种新兴的非易失性存储器（NVM）技术，因其能够克服传统CMOS技术的缺陷而受到关注。然而，此类技术必须在实际工作负载和架构部署前进行评估。目前缺乏可用的开源STT-RAM系统评估框架，这阻碍了相关研究与实验，并影响了STT-RAM在系统中的采用。本文提出了一种新颖且可扩展的STT-RAM内存控制器设计，并将其集成到gem5仿真器中。我们的框架能够从功耗、延迟、时钟周期、能量及系统吞吐量等多个维度深入理解STT-RAM。我们将开源该HOPE框架，以推动研究进展并加速基于STT-RAM的未来系统架构开发，同时方便用户对工具进行进一步扩展。