Automating hardware (HW) security vulnerability detection and mitigation during the design phase is imperative for two reasons: (i) It must be before chip fabrication, as post-fabrication fixes can be costly or even impractical; (ii) The size and complexity of modern HW raise concerns about unknown vulnerabilities compromising CIA triad. While Large Language Models (LLMs) can revolutionize both HW design and testing processes, within the semiconductor context, LLMs can be harnessed to automatically rectify security-relevant vulnerabilities inherent in HW designs. This study explores the seeds of LLM integration in register transfer level (RTL) designs, focusing on their capacity for autonomously resolving security-related vulnerabilities. The analysis involves comparing methodologies, assessing scalability, interpretability, and identifying future research directions. Potential areas for exploration include developing specialized LLM architectures for HW security tasks and enhancing model performance with domain-specific knowledge, leading to reliable automated security measurement and risk mitigation associated with HW vulnerabilities.

翻译：在硬件（HW）设计阶段实现安全漏洞自动化检测与缓解至关重要，原因有二：（i）必须在芯片制造前完成，因为制造后的修复成本高昂甚至不切实际；（ii）现代硬件规模和复杂性令人担忧，未知漏洞可能破坏机密性、完整性和可用性（CIA三元组）。虽然大语言模型（LLM）能够彻底改变硬件设计与测试流程，但在半导体领域，LLM可被用于自动纠正硬件设计中固有关联的安全漏洞。本研究探讨LLM在寄存器传输级（RTL）设计中的集成萌芽，重点关注其自主解决安全相关漏洞的能力。分析涉及方法比较、可扩展性与可解释性评估，以及未来研究方向识别。潜在探索领域包括：开发面向硬件安全任务的专用LLM架构，通过领域特定知识增强模型性能，最终实现与硬件漏洞相关的可靠自动化安全度量和风险缓解。