Weak memory models allow for simplified hardware and increased performance in the memory hierarchy at the cost of increased software complexity. In weak memory models, explicit synchronization is needed to enforce ordering between different processors. Acquire and release semantics provide a powerful primitive for expressing only the ordering required for correctness. In this project, we explore adding load-acquire and store-release instructions to the RISC-V ISA. We add support to the herd formal memory model, the gem5 cycle-approximate simulator, and the LLVM/Clang toolchain. Because these instructions do not exist in the RISC-V standard, there is an inherent urgency to ratify explicit load-acquire/store-release instructions in order to prevent multiple ABI implementations and ecosystem fragmentation. We found that for workloads with a high degree of sharing and heavy contention, the impact of less memory ordering is muted, but our changes successfully encode the semantics we desire.

翻译：弱内存模型通过降低硬件复杂度并提升内存层次结构中的性能，但代价是增加了软件复杂性。在弱内存模型中，需要显式同步来强制不同处理器之间的执行顺序。获取（Acquire）与释放（Release）语义提供了一种强大的原语，能够仅表达正确性所需的排序约束。在本项目中，我们探索了向RISC-V指令集架构（ISA）添加加载-获取（load-acquire）与存储-释放（store-release）指令的方法。我们在herd形式化内存模型、gem5周期近似模拟器以及LLVM/Clang工具链中添加了相应支持。由于这些指令尚未存在于RISC-V标准中，为了阻止多个应用二进制接口（ABI）实现及生态系统碎片化，亟需批准显式加载-获取/存储-释放指令。我们发现，对于具有高共享度和严重竞争的工作负载，减少内存排序的影响较为有限，但我们的更改成功编码了所需的语义。