As the number of cores scale to tens and hundreds, the energy consumption of routers across various types of on-chip networks in chip muiltiprocessors (CMPs) increases significantly. A major source of this energy consumption comes from the input buffers inside Network-on-Chip (NoC) routers, which are traditionally designed to maximize performance. To mitigate this high energy cost, many works propose bufferless router designs that utilize deflection routing to resolve port contention. While this approach is able to maintain high performance relative to its buffered counterparts at low network traffic, the bufferless router design suffers performance degradation under high network load. In order to maintain high performance and energy efficiency under both low and high network loads, this chapter discusses critical drawbacks of traditional bufferless designs and describes recent research works focusing on two major modifications to improve the overall performance of the traditional bufferless network-on-chip design. The first modification is a minimally-buffered design that introduces limited buffering inside critical parts of the on-chip network in order to reduce the number of deflections. The second modification is a hierarchical bufferless interconnect design that aims to further improve performance by limiting the number of hops each packet needs to travel while in the network. In both approaches, we discuss design tradeoffs and provide evaluation results based on common CMP configurations with various network topologies to show the effectiveness of each proposal.

翻译：由于核心规模达到数十个和数百个,各种芯片处理器芯片混凝土处理器(CMPs)中各种类型的芯片网络中路由器的能源消耗量大幅增加,这种能源消耗的一个主要来源是网络-芯片网络(NOC)路由器内的投入缓冲器,传统上设计这些缓冲器是为了最大限度地提高性能。为了减轻这种高能源成本,许多工程提议采用无缓冲路由器设计,利用偏转路由解决港口争议。虽然这种方法能够保持相对于网络交通量低的缓冲对等器的高度性能,但缓冲路由器设计在高网络负荷下受到性能退化的影响。为了在低网络负荷和高网络负荷下保持高性能和能效,本章讨论了传统无缓冲设计路由器路由器路由器路由器路由器路由器中的关键性能。本章讨论了传统无缓冲设计的关键缺陷,并介绍了近期的研究工作,重点是改进传统的无缓冲网络-电路由设计的总体性能。第一次修改是最小的设计的缓冲设计,目的是减少顶网络内部关键部分的缓冲性能,以减少偏偏差量。第二次修改是每级缓冲网络的设计,同时讨论各种模式设计,目的是改进共同设计。