Nanometer scale power amplifiers (PA) at sub-THz suffer from severe parasitic effects that lead to experience limited maximum frequency and reduced power performance at the device transceiver front end. The integrated circuits researchers proposed different PA design architecture combinations at scaled down technologies to overcome these limitations. Although the designs meet the minimum requirements, the power added efficiency (PAE) of PA is still quite low. In this paper, a W-band single-ended common-source (CS) and cascode integrated 3-stage 2-way PA design is proposed. The design integrated different key design methodologies to mitigate the parasitic; such as combined Class AB and Class A stages for gain-boosting and efficiency enhancement, Wilkinson power combiner for higher output power, linearity, and bandwidth, and transmission line (TL)-based wide band matching network for better inter-stage matching and compact size. The proposed PA design is validated using UMS 150-nm GaAs pHEMT using advanced design system (ADS) simulator. The results show that the proposed PA achieved a gain of 20.1 dB, an output power of 17.2 dBm, a PAE of 33 % and a 21 GHz bandwidth at 90 GHz Sub-THz band. The PA layout consumes only 5.66 X 2.51 mm2 die space including pads. Our proposed PA design will boost the research on sub-THz integrated circuits research and will smooth the wide spread adoption of 6G in near future.

翻译：亚THz频段的纳米级功率放大器因遭受严重的寄生效应，导致器件收发前端面临最大频率受限和功率性能下降的问题。集成电路研究者提出不同缩放工艺下的功放架构组合设计来克服这些限制。尽管现有设计达到最低要求，但功放的功率附加效率(PAE)仍然较低。本文提出一种W波段单端共源(CS)与共源共栅集成式三级两路功放设计。该设计融合多种关键方法来抑制寄生效应：采用Class AB与Class A级联实现增益提升与效率增强，利用威尔金森功率合成器提高输出功率、线性度及带宽，并基于传输线(TL)宽频匹配网络实现级间匹配优化与紧凑尺寸。通过先进设计系统(ADS)仿真器在UMS 150nm GaAs pHEMT工艺上验证所提出的功放设计。结果表明，该功放在90 GHz亚THz频段实现增益20.1 dB、输出功率17.2 dBm、PAE达33%及21 GHz带宽。功放版图（含焊盘）仅占用5.66×2.51 mm²芯片面积。所提出的功放设计将推动亚THz集成电路研究，并助力6G技术在近期的广泛应用。