Floating point arithmetic remains expensive on FPGA platforms due to wide datapaths and normalization logic, motivating alternative representations that preserve dynamic range at lower cost. This work introduces the Hybrid Residue Floating Numerical Architecture (HRFNA), a unified arithmetic system that combines carry free residue channels with a lightweight floating point scaling factor. We develop the full mathematical framework, derive bounded error normalization rules, and present FPGA optimized microarchitectures for modular multiplication, exponent management, and hybrid reconstruction. HRFNA is implemented on a Xilinx ZCU104, with Vitis simulation, RTL synthesis, and on chip ILA traces confirming cycle accurate correctness. The architecture achieves over 2.1 times throughput improvement and 38-52 percent LUT reduction compared to IEEE 754 single precision baselines while maintaining numerical stability across long iterative sequences. These results demonstrate that HRFNA offers an efficient and scalable alternative to floating point computation on modern FPGA devices.

翻译：由于宽数据通路和归一化逻辑的存在，浮点算术在FPGA平台上仍具有较高开销，这促使人们寻求在较低成本下保持动态范围的替代表示方法。本文提出混合余数浮点数值架构（HRFNA），这是一种将无进位余数通道与轻量级浮点缩放因子相结合的统一算术系统。我们建立了完整的数学框架，推导出有界误差归一化规则，并提出了针对模乘运算、指数管理和混合重构的FPGA优化微架构。HRFNA在Xilinx ZCU104平台上实现，通过Vitis仿真、RTL综合和片上ILA跟踪验证了周期级精度正确性。该架构在保持长迭代序列数值稳定性的同时，相比IEEE 754单精度基准实现了超过2.1倍的吞吐量提升和38-52%的LUT资源缩减。这些结果表明，HRFNA为现代FPGA设备提供了一种高效且可扩展的浮点计算替代方案。