Large Language Models (LLMs) have demonstrated capabilities for producing code in Hardware Description Languages (HDLs). However, most of the focus remains on their abilities to write functional code, not test code. The hardware design process consists of both design and test, and so eschewing validation and verification leaves considerable potential benefit unexplored, given that a design and test framework may allow for progress towards full automation of the digital design pipeline. In this work, we perform one of the first studies exploring how a LLM can both design and test hardware modules from provided specifications. Using a suite of 8 representative benchmarks, we examined the capabilities and limitations of the state-of-the-art conversational LLMs when producing Verilog for functional and verification purposes. We taped out the benchmarks on a Skywater 130nm shuttle and received the functional chip.

翻译：大型语言模型（LLMs）已展现出生成硬件描述语言（HDLs）代码的能力。然而，当前研究大多聚焦于其编写功能代码的能力，而非测试代码。硬件设计流程包含设计与测试两个环节，若忽略验证与确认，则意味着大量潜在效益未被挖掘——因为设计与测试框架的完善可能推动数字设计流程迈向全自动化。本研究首次探索了LLM如何根据给定规格同时完成硬件模块的设计与测试。通过8个代表性基准测试用例，我们分析了最先进的对话式LLM在生成功能性及验证性Verilog代码时的能力与局限性。我们将这些基准设计流片至Skywater 130nm工艺节点，并成功获得功能正常的芯片。