This paper presents a mixed-signal neuromorphic accelerator architecture designed for accelerating inference with event-based neural network models. This fully CMOS-compatible accelerator utilizes analog computing to emulate synapse and neuron operations. A C2C ladder structure implements synapses, while operational amplifiers (op-amps) are used to realize neuron functions. To enhance hardware resource utilization and power efficiency, we introduce the concept of a virtual neuron, where a single neuron engine emulates a set of model neurons, leveraging the sparsity inherent in event-based neuromorphic systems. Additionally, we propose a memory-based control technique to manage events in each layer, which improves performance while maintaining the flexibility to support various layer types. We also introduce an integer linear programming (ILP)-based mapping approach for efficiently allocating the model onto the proposed accelerator. The accelerator is a general-purpose neuromorphic platform capable of executing linear and convolutional neural models. The effectiveness of the proposed architecture is evaluated using two specially designed neuromorphic accelerators and two event-based datasets. The results show that the proposed architecture achieves 12.1 TOPS/W energy efficiency when accelerating a model trained on CIFAR10-DVS.

翻译：本文提出一种混合信号神经形态加速器架构，专为加速基于事件的神经网络模型推理而设计。该加速器完全兼容CMOS工艺，利用模拟计算来模拟突触和神经元操作。其中，突触通过C2C梯形结构实现，而神经元功能则通过运算放大器实现。为提高硬件资源利用率和能效，我们引入虚拟神经元概念，即单个神经元引擎通过利用事件驱动神经形态系统固有的稀疏性，来模拟一组模型神经元。此外，我们提出一种基于存储器的控制技术来管理每层的事件，该技术在保持支持多种层类型灵活性的同时提升了性能。我们还提出一种基于整数线性规划的映射方法，用于将模型高效部署到所提出的加速器上。该加速器作为通用神经形态平台，能够执行线性和卷积神经模型。我们使用两个专门设计的神经形态加速器和两个基于事件的数据集评估了所提架构的有效性。结果表明，在加速基于CIFAR10-DVS训练的模型时，该架构实现了12.1 TOPS/W的能效。