Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make the approach more feasible. We present a concrete example by demonstrating how FPGA technology mappers can be automatically generated from SystemVerilog models of an FPGA's primitives using program synthesis.

翻译：编译器后端应从其目标硬件的硬件设计语言（HDL）模型自动生成。直接从HDL生成编译器组件可提供更强的正确性保证、减轻开发工作，并促进硬件探索。以往研究已倡导这一思路；在此我们论证，程序合成领域的进展使该方法更具可行性。我们通过具体实例展示：利用程序合成技术，如何从FPGA原语的SystemVerilog模型自动生成FPGA技术映射器。