Large Language Models (LLMs) have demonstrated capabilities for producing code in Hardware Description Languages (HDLs). However, most of the focus remains on their abilities to write functional code, not test code. The hardware design process consists of both design and test, and so eschewing validation and verification leaves considerable potential benefit unexplored, given that a design and test framework may allow for progress towards full automation of the digital design pipeline. In this work, we perform one of the first studies exploring how a LLM can both design and test hardware modules from provided specifications. Using a suite of 8 representative benchmarks, we examined the capabilities and limitations of the state-of-the-art conversational LLMs when producing Verilog for functional and verification purposes. We taped out the benchmarks on a Skywater 130nm shuttle and received the functional chip.

翻译：大型语言模型（LLMs）已展现出生成硬件描述语言（HDLs）代码的能力。然而，现有研究大多关注其编写功能代码的能力，而非测试代码。硬件设计流程包含设计与测试两个环节，若忽略验证与确认，将无法充分挖掘其潜在价值——因为一个完整的设计与测试框架可能推动数字设计流程实现全面自动化。本研究率先探索了大型语言模型如何根据给定规格同时设计并测试硬件模块。通过使用包含8个代表性基准测试的测试集，我们考察了当前最先进的对话式大型语言模型在生成用于功能实现与验证的Verilog代码时的能力与局限性。我们在Skywater 130nm工艺流片上完成了这些基准测试的设计制造，并获得了可正常工作的芯片。