Configuration-induced perturbations in SRAM-based FPGAs may activate dormant programmable routing branches and increase path delay without immediately producing a functional error. Although prior studies have separately investigated the electrical origin of these delay changes, their in-situ detection, and the topology of commercial routing fabrics, a scalable method for predicting their timing impact at the granularity of programmable interconnect points and routed nets remains unavailable. This paper presents GRACIDIT, a graph-circuit digital twin framework for predicting configuration-induced routing delay degradation in Zynq UltraScale+ FPGAs. The proposed framework extracts the routing-resource graph of the XCZU7EV programmable fabric from the vendor design database, identifies inactive programmable interconnect points adjacent to active routes, and represents each candidate perturbation through its branch topology, geometric span, fan-out, physical region, and downstream loading. These graph features are combined with a calibrated reduced-order electrical model to estimate the delay introduced by single and cumulative routing-branch activations. Controlled configuration-equivalent perturbations are generated on a ZCU104 platform and characterized using complementary routing-domain oscillators and phase-sweep probes. The resulting model associates predicted delay shifts with available timing slack to rank vulnerable programmable interconnect points and routed nets and to construct a spatial vulnerability atlas of the programmable fabric. Experimental evaluation demonstrates a mean absolute prediction error of 7.8 ps, achieves 87.4 percent recall for slack-violating perturbations, and attains a Recall at 10 value of 0.90 for the most vulnerable routing resources.

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