Generation and exploration of approximate circuits and accelerators has been a prominent research domain to achieve energy-efficiency and/or performance improvements. This research has predominantly focused on ASICs, while not achieving similar gains when deployed for FPGA-based accelerator systems, due to the inherent architectural differences between the two. In this work, we propose a novel framework, Xel-FPGAs, which leverages statistical or machine learning models to effectively explore the architecture-space of state-of-the-art ASIC-based approximate circuits to cater them for FPGA-based systems given a simple RTL description of the target application. We have also evaluated the scalability of our framework on a multi-stage application using a hierarchical search strategy. The Xel-FPGAs framework is capable of reducing the exploration time by up to 95%, when compared to the default synthesis, place, and route approaches, while identifying an improved set of Pareto-optimal designs for a given application, when compared to the state-of-the-art. The complete framework is open-source and available online at https://github.com/ehw-fit/xel-fpgas.

翻译：近似电路与加速器的生成及探索已成为实现能效提升和/或性能改进的重要研究领域。由于ASIC与FPGA加速器系统在架构上的本质差异，该研究主要聚焦于专用集成电路（ASIC），但在部署至FPGA系统时未能取得同等增益。本文提出一种名为Xel-FPGAs的新型框架，该框架利用统计模型或机器学习模型，基于目标应用的简单RTL描述，有效探索现有基于ASIC的近似电路的架构空间，使其适配于FPGA系统。我们还采用分层搜索策略，在多阶段应用上评估了该框架的可扩展性。与默认的综合、布局布线方法相比，Xel-FPGAs框架能够将探索时间减少高达95%，同时相较于现有技术，可为给定应用识别出更优的帕累托最优设计集合。该完整框架为开源项目，可通过https://github.com/ehw-fit/xel-fpgas在线获取。