By exploiting the modular RISC-V ISA this paper presents the customization of instruction set with posit\textsuperscript{\texttrademark} arithmetic instructions to provide improved numerical accuracy, well-defined behavior and increased range of representable numbers while keeping the flexibility and benefits of open-source ISA, like no licensing and royalty fee and community development. In this work we present the design, implementation and integration into the low-power Ibex RISC-V core of a full posit processing unit capable to directly implement in hardware the four arithmetic operations (add, sub, mul, div and fma), the inversion, the float-to-posit and posit-to-float conversions. We evaluate speed, power and area of this unit (that we have called Full Posit Processing Unit). The FPPU has been prototyped on Alveo and Kintex FPGAs, and its impact on the metrics of the full-RISC-V core have been evaluated, showing that we can provide real number processing capabilities to the mentioned core with an increase in area limited to $7\%$ for 8-bit posits and to $15\%$ for 16-bit posits. Finally we present tests one the use of posits for deep neural networks with different network models and datasets, showing minimal drop in accuracy when using 16-bit posits instead of 32-bit IEEE floats.

翻译：本文利用模块化RISC-V指令集架构，通过引入正数（posit\textsuperscript{\texttrademark}）算术指令扩展指令集，在保持开源指令集灵活性、免许可费与免版税及社区开发等优势的同时，提供更高的数值精度、明确的行为定义以及更广的可表示数值范围。本研究提出了一种全正数处理单元（Full Posit Processing Unit）的设计、实现及其与低功耗Ibex RISC-V内核的集成方案，该单元能够通过硬件直接实现四种算术运算（加、减、乘、除及乘加融合）、倒数运算、浮点数与正数之间的格式转换。我们对该单元（命名为FPPU）的速度、功耗及面积进行了评估。FPPU已在Alveo与Kintex FPGA上完成原型验证，并评估了其对完整RISC-V内核性能指标的影响。结果表明，该单元可为上述内核提供实数处理能力，且面积增加在8位正数场景下不超过$7\%$，在16位正数场景下不超过$15\%$。最后，我们通过不同网络模型与数据集测试了正数在深度神经网络中的应用，证明采用16位正数替代32位IEEE浮点数时，精度损失极小。