Quantum computing is in an era defined by rapidly evolving quantum hardware technologies, combined with persisting high gate error rates, large amounts of noise, and short coherence times. Overcoming these limitations requires systems-level approaches that account for the strengths and weaknesses of the underlying hardware technology. Yet few hardware-aware compiler techniques exist for neutral atom devices, with no prior work on compiling to the neutral atom native gate set. In particular, current neutral atom hardware does not support certain single-qubit rotations via local addressing, which often requires the circuit to be decomposed into a large number of gates, leading to long circuit durations and low overall fidelities. We propose the first compiler designed to overcome the challenges of limited local addressibility in neutral atom quantum computers. We present algorithms to decompose circuits into the neutral atom native gate set, with emphasis on optimizing total pulse area of global gates, which dominate gate execution costs in several current architectures. Furthermore, we explore atom movement as an alternative to expensive gate decompositions, gaining immense speedup with routing, which remains a huge overhead for many quantum circuits. Our decomposition optimizations result in up to ~3.5x and ~2.9x speedup in time spent executing global gates and time spent executing single-qubit gates, respectively. When combined with our atom movement routing algorithms, our compiler achieves up to ~10x reduction in circuit duration, with over ~2x improvement in fidelity. We show that our compiler strategies can be adapted for a variety of hardware-level parameters as neutral atom technology continues to develop.

翻译：量子计算正处于量子硬件技术快速演进的时代，但面临高门错误率、大量噪声和短相干时间等持续挑战。克服这些局限需要从系统级角度考虑底层硬件技术的优势与不足。然而，目前针对中性原子器件的硬件感知编译技术较少，且尚无相关研究探讨如何编译至中性原子原生门集。特别是当前的中性原子硬件无法通过局域寻址实现特定单量子比特旋转，这常导致电路需分解为大量门操作，造成电路执行时间长、整体保真度低。我们提出首个针对中性原子量子计算机中局域寻址能力受限难题的编译器，首次给出将电路分解为中性原子原生门集的算法，并着重优化全局门的脉冲总面积——该指标在多个现有架构中主导门执行成本。此外，我们探索以原子移动替代高成本的复杂门分解，通过路由技术获得显著加速，而路由问题目前仍是许多量子电路的巨大开销。我们的分解优化使全局门执行时间与单量子比特门执行时间分别提升约3.5倍和2.9倍。结合原子移动路由算法后，编译器实现了电路时长最高约10倍的缩减，保真度提升超过2倍。研究表明，随着中性原子技术持续发展，我们的编译策略可适配多种硬件参数。