The increasing growth of applications' memory capacity and performance demands has led the CPU vendors to deploy heterogeneous memory systems either within a single system or via disaggregation. For instance, systems like Intel's Knights Landing and Sapphire Rapids can be configured to use high bandwidth memory as a cache to main memory. While there is significant research investigating the designs of DRAM caches, there has been little research investigating DRAM caches from a full system point of view, because there is not a suitable model available to the community to accurately study largescale systems with DRAM caches at a cycle-level. In this work we describe a new cycle-level DRAM cache model in the gem5 simulator which can be used for heterogeneous and disaggregated systems. We believe this model enables the community to perform a design space exploration for future generation of memory systems supporting DRAM caches.

翻译：随着应用对内存容量和性能需求的不断增长，CPU厂商开始在单一系统内或通过解耦方式部署异构内存系统。例如，英特尔的Knights Landing和Sapphire Rapids系统可配置为将高带宽内存作为主内存的缓存。尽管已有大量研究探讨DRAM缓存的设计，但鲜有研究从全系统视角审视DRAM缓存，这是因为目前社区缺乏合适的模型来精确模拟包含DRAM缓存的大规模系统在周期级的行为。本文在gem5模拟器中描述了一种新的周期级DRAM缓存模型，该模型可用于异构和解耦系统。我们相信，该模型将使社区能够为支持DRAM缓存的下一代内存系统开展设计空间探索。