Memory disaggregation is being considered as a strong alternative to traditional architecture to deal with the memory under-utilization in data centers. Disaggregated memory can adapt to dynamically changing memory requirements for the data center applications like data analytics, big data, etc., that require in-memory processing. However, such systems can face high remote memory access latency due to the interconnect speeds. In this paper, we explore a rack-scale disaggregated memory architecture and discuss the various design aspects. We design a trace-driven simulator that combines an event-based interconnect and a cycle-accurate memory simulator to evaluate the performance of disaggregated memory system at the rack scale. Our study shows that not only the interconnect but the contention in the remote memory queues also adds significantly to remote memory access latency. We introduces a memory allocation policy to reduce the latency compared to the conventional policies. We conduct experiments using various benchmarks with diverse memory access patterns. Our study shows encouraging results towards the rack-scale memory disaggregation and acceptable average memory access latency.

翻译：内存解耦正被视为传统架构的有力替代方案，以应对数据中心中内存利用率低下的问题。解耦内存能够适应数据分析和大数据等需要内存处理的数据中心应用对内存需求的动态变化。然而，由于互连速度的限制，此类系统可能面临较高的远程内存访问延迟。在本文中，我们探索了一种机架级解耦内存架构，并讨论了其各种设计方面。我们设计了一个基于踪迹的模拟器，该模拟器结合了基于事件的互连模型和周期精确的内存模拟器，以评估机架级解耦内存系统的性能。我们的研究表明，不仅互连本身，远程内存队列中的竞争也会显著增加远程内存访问延迟。我们引入了一种内存分配策略，相较于传统策略能够降低延迟。我们使用具有不同内存访问模式的多种基准测试进行了实验。研究结果表明，机架级内存解耦具有广阔前景，且平均内存访问延迟在可接受范围内。