We investigate the complexity of uniform OR circuits and AND circuits of polynomial-size and depth. As their name suggests, OR circuits have OR gates as their computation gates, as well as the usual input, output and constant (0/1) gates. As is the norm for Boolean circuits, our circuits have multiple sink gates, which implies that an OR circuit computes an OR function on some subset of its input variables. Determining that subset amounts to solving a number of reachability questions on a polynomial-size directed graph (which input gates are connected to the output gate?), taken from a very sparse set of graphs. However, it is not obvious whether or not this (restricted) reachability problem can be solved, by say, uniform AC^0 circuits (constant depth, polynomial-size, AND, OR, NOT gates). This is one reason why characterizing the power of these simple-looking circuits in terms of uniform classes turns out to be intriguing. Another is that the model itself seems particularly natural and worthy of study. Our goal is the systematic characterization of uniform polynomial-size OR circuits, and AND circuits, in terms of known uniform machine-based complexity classes. In particular, we consider the languages reducible to such uniform families of OR circuits, and AND circuits, under a variety of reduction types. We give upper and lower bounds on the computational power of these language classes. We find that these complexity classes are closely related to tallyNL, the set of unary languages within NL, and to sets reducible to tallyNL. Specifically, for a variety of types of reductions (many-one, conjunctive truth table, disjunctive truth table, truth table, Turing) we give characterizations of languages reducible to OR circuit classes in terms of languages reducible to tallyNL classes. Then, some of these OR classes are shown to coincide, and some are proven to be distinct. We give analogous results for AND circuits. Finally, for many of our OR circuit classes, and analogous AND circuit classes, we prove whether or not the two classes coincide, although we leave one such inclusion open.

翻译：我们调查了统一或电路的复杂性,以及多元大小和深度的电路和电路的复杂性。 正如其名称所示, 或电路有或有门作为计算门, 以及通常的输入、 输出和常数( 0/1) / / 门。 正如布利安电路的规范一样, 我们的电路有多个水槽门, 这意味着一个电路在其输入变量的某个子集中计算了一个或功能。 确定该子可以解决一个多元大小的定向图形( 输入门与输出门连接? ) 上的可达性问题。 从一个非常稀少的图表中取出。 然而, 这个( 限制的) 通电路门和常数( 限制的) 能否通过统一的 AC- 0 电路路路路的规范( 等深度、 多元规模、 或 点门的门 ) 。 这就是为什么将这些简单电路的电路的电路的电路转换到直通到直通的电路流, 我们的电路的变变变变变的变变变变变。 和变变变变的变的变变的变的变变变的变, 我们的变变的变的变更变更变的变, 我们的变的变的变的变的变的变的变变的变的变的变的变的变更变更的变的变的变的变, 变的变的变的变的变的变的变的变的变, 变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变的变