A chiplet is an integrated circuit that encompasses a well-defined subset of an overall system's functionality. In contrast to traditional monolithic system-on-chips (SoCs), chiplet-based architecture can reduce costs and increase reusability, representing a promising avenue for continuing Moore's Law. Despite the advantages of multi-chiplet architectures, floorplan design in a chiplet-based architecture has received limited attention. Conflicts between cost and performance necessitate a trade-off in chiplet floorplan design since additional latency introduced by advanced packaging can decrease performance. Consequently, balancing power, performance, cost, area, and reliability is of paramount importance. To address this challenge, we propose Floorplet, a framework comprising simulation tools for performance reporting and comprehensive models for cost and reliability optimization. Our framework employs the open-source Gem5 simulator to establish the relationship between performance and floorplan for the first time, guiding the floorplan optimization of multi-chiplet architecture. The experimental results show that our framework decreases inter-chiplet communication costs by 24.81%.

翻译：芯粒是集成电路中实现整体系统功能明确定义子集的单元。相较于传统单芯片系统级芯片（SoC），基于芯粒的架构能够降低成本并提升复用性，为延续摩尔定律提供了可行路径。尽管多芯粒架构具备优势，但芯粒架构中的布图规划设计尚未得到充分研究。由于先进封装引入的额外延迟可能降低性能，成本与性能之间的矛盾使得芯粒布图设计需要权衡。因此，平衡功耗、性能、成本、面积与可靠性至关重要。针对这一挑战，我们提出Floorplet框架，该框架包含用于性能报告的仿真工具以及用于成本与可靠性优化的综合模型。本框架首次采用开源Gem5模拟器建立性能与布图规划之间的关联，从而指导多芯粒架构的布图规划优化。实验结果表明，该框架将芯粒间通信成本降低了24.81%。