Printed circuit boards (PCBs) are an integral part of electronic systems. Hence, verifying their physical integrity in the presence of supply chain attacks (e.g., tampering and counterfeiting) is of utmost importance. Recently, tamper detection techniques grounded in impedance characterization of PCB's Power Delivery Network (PDN) have gained prominence due to their global detection coverage, non-invasive, and low-cost nature. Similar to other physical verification methods, these techniques rely on the existence of a physical golden sample for signature comparisons. However, having access to a physical golden sample for golden signature extraction is not feasible in many real-world scenarios. In this work, we assess the feasibility of eliminating a physical golden sample and replacing it with a simulated golden signature obtained by the PCB design files. By performing extensive simulation and measurements on an in-house designed PCB, we demonstrate how the parasitic impedance of the PCB components plays a major role in reaching a successful verification. Based on the obtained results and using statistical metrics, we show that we can mitigate the discrepancy between collected signatures from simulation and measurements.

翻译：印刷电路板（PCB）是电子系统的重要组成部分。因此，在供应链攻击（如篡改和伪造）存在的情况下，验证其物理完整性至关重要。近年来，基于PCB电源分配网络（PDN）阻抗表征的篡改检测技术因其全局检测覆盖范围、非侵入性和低成本特性而备受关注。与其他物理验证方法类似，这些技术依赖物理黄金样本进行签名比对。然而，在许多实际场景中，获取物理黄金样本以提取黄金签名并不可行。本研究评估了消除物理黄金样本并将其替换为由PCB设计文件获得的仿真黄金签名的可行性。通过对自主设计的PCB进行大量仿真与测量，我们展示了PCB组件的寄生阻抗在达成成功验证中起关键作用。基于所得结果并运用统计指标，我们证明能够缩小仿真与测量采集签名之间的差异。