With the recent release of High Bandwidth Memory (HBM) based FPGA boards, developers can now exploit unprecedented external memory bandwidth. This allows more memory-bounded applications to benefit from FPGA acceleration. However, we found that it is not easy to fully utilize the available bandwidth when developing some applications with high-level synthesis (HLS) tools. This is due to the limitation of existing HLS tools when accessing HBM board's large number of independent external memory channels. In this paper, we measure the performance of three recent representative HBM FPGA boards (Intel's Stratix 10 MX and Xilinx's Alveo U50/U280 boards) with microbenchmarks and analyze the HLS overhead. Next, we propose HLS-based optimization techniques to improve the effective bandwidth when a PE accesses multiple HBM channels or multiple PEs access an HBM channel. Our experiment demonstrates that the effective bandwidth improves by 2.4X-3.8X. We also provide a list of insights for future improvement of the HBM FPGA HLS design flow.

翻译：由于最近发布了基于高宽带内存(HBM)的FPGA板,开发商现在可以利用史无前例的外部内存带宽,这样可以让更多的内存应用程序受益于FPGA加速。然而,我们发现,在开发一些具有高级合成工具的应用程序时,很难充分利用现有的带宽。这是因为在访问HBM董事会大量独立的外部内存渠道时,现有的HLS工具受到限制。在本文中,我们测量了最近三个具有代表性的HBM FPGA板(Intel's Stratix 10 MX和Xilinx's Alveo U50/U280 板)的性能,它们使用微调标记,分析HLS的间接费用。接下来,我们提出基于HLS的优化技术,以便在PE访问多个HBM频道或多个PE进入HBM频道时改进有效的带宽。我们的实验表明,有效的带宽在2.4X-3.8X上得到了改进。我们还提供了未来改进HBM FPGA HLS设计流程的见解清单。