The utilization of finite field multipliers is pervasive in contemporary digital systems, with hardware implementation for bit parallel operation often necessitating millions of logic gates. However, various digital design issues, whether natural or stemming from soft errors, can result in gate malfunction, ultimately leading to erroneous multiplier outputs. Thus, to prevent susceptibility to error, it is imperative to employ an effective finite field multiplier implementation that boasts a robust fault detection capability. This study proposes a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), intended to achieve optimal fault detection performance for finite field multipliers while simultaneously maintaining a low-complexity implementation, a favored attribute in resource-constrained applications like smart cards. The primary concept behind the proposed approach is centered on the implementation of a BCH decoder that utilizes re-encoding technique and FIBM algorithm in its first and second sub-modules, respectively. This approach serves to address hardware complexity concerns while also making use of Berlekamp-Rumsey-Solomon (BRS) algorithm and Chien search method in the third sub-module of the decoder to effectively locate errors with minimal delay. The results of our synthesis indicate that our proposed error detection and correction architecture for a 45-bit multiplier with 5-bit errors achieves a 37% and 49% reduction in critical path delay compared to existing designs. Furthermore, the hardware complexity associated with a 45-bit multiplicand that contains 5 errors is confined to a mere 80%, which is significantly lower than the most exceptional BCH-based fault recognition methodologies, including TMR, Hamming's single error correction, and LDPC-based procedures within the realm of finite field multiplication.

翻译：有限域乘法器在现代数字系统中应用广泛，其硬件实现位并行运算通常需要数百万逻辑门。然而，各种数字设计问题（无论是自然原因还是由软错误引起）都可能导致门级故障，最终使乘法器输出错误。因此，为防止对错误的敏感性，必须采用具备强大故障检测能力的有效有限域乘法器实现方案。本研究针对GF(2m)上一种新型位并行多项式基乘法器，提出了一种新颖的故障检测方案，旨在实现有限域乘法器的最优故障检测性能，同时保持低复杂度的实现——这一特性在智能卡等资源受限应用中备受青睐。所提方法的核心思路在于实现一个BCH解码器，其第一子模块和第二子模块分别采用重新编码技术和FIBM算法。该方案通过利用第三子模块中的Berlekamp-Rumsey-Solomon（BRS）算法和钱氏搜索方法，在最小延迟内有效定位错误，从而解决硬件复杂度问题。综合结果表明，针对支持5位错误校正的45位乘法器，所提出的错误检测与校正架构的关键路径延迟相比现有设计降低了37%和49%。此外，对于包含5位错误的45位被乘数，其硬件复杂度仅控制在80%，远优于有限域乘法领域中最优秀的BCH故障识别方法（包括TMR、汉明单错误校正及基于LDPC的流程）。