FPGA acceleration is becoming increasingly important to meet the performance demands of modern computing, particularly in big data or machine learning applications. As such, significant effort is being put into the optimization of the hardware accelerators. However, integrating accelerators into modern FPGA platforms, with key features such as high bandwidth memory (HBM), requires manual effort from a platform expert for every new application. We propose the Olympus multi-level intermediate representation (MLIR) dialect and Olympus-opt, a series of analysis and transformation passes on this dialect, for representing and optimizing platform aware system level FPGA architectures. By leveraging MLIR, our automation will be extensible and reusable both between many sources of input and many platform-specific back-ends.

翻译：FPGA加速在现代计算（尤其是大数据或机器学习应用）中满足性能需求方面日益重要。因此，大量研究致力于硬件加速器的优化。然而，将加速器集成到具有高带宽存储器（HBM）等关键特性的现代FPGA平台中，需要平台专家为每个新应用进行手动操作。我们提出了Olympus多层次中间表示（MLIR）方言及Olympus-opt（一系列基于该方言的分析与变换过程），用于表示和优化平台感知的系统级FPGA架构。通过利用MLIR，我们的自动化方案可在多种输入源与多种特定平台后端之间实现可扩展性与可重用性。