The increasing adoption of Deep Neural Network (DNN)-based Digital Pre-distortion (DPD) in modern communication systems necessitates efficient hardware implementations. This paper presents DPD-NeuralEngine, an ultra-fast, tiny-area, and power-efficient DPD accelerator based on a Gated Recurrent Unit (GRU) neural network (NN). Leveraging a co-designed software and hardware approach, our 22 nm CMOS implementation operates at 2 GHz, capable of processing I/Q signals up to 250 MSps. Experimental results demonstrate a throughput of 256.5 GOPS and power efficiency of 1.32 TOPS/W with DPD linearization performance measured in Adjacent Channel Power Ratio (ACPR) of -45.3 dBc and Error Vector Magnitude (EVM) of -39.8 dB. To our knowledge, this work represents the first AI-based DPD application-specific integrated circuit (ASIC) accelerator, achieving a power-area efficiency (PAE) of 6.6 TOPS/W/mm$^2$.

翻译：现代通信系统中基于深度神经网络（DNN）的数字预失真（DPD）技术日益普及，这对其高效的硬件实现提出了迫切需求。本文提出DPD-NeuralEngine，一款基于门控循环单元（GRU）神经网络（NN）的超高速、超小面积、高能效的DPD加速器。通过采用软硬件协同设计方法，我们在22纳米CMOS工艺下实现的芯片工作频率达到2 GHz，能够处理高达250 MSps的I/Q信号。实验结果表明，该加速器的吞吐量为256.5 GOPS，能效为1.32 TOPS/W，其DPD线性化性能以邻道功率比（ACPR）和误差矢量幅度（EVM）衡量，分别达到-45.3 dBc和-39.8 dB。据我们所知，这是首款基于人工智能的DPD专用集成电路（ASIC）加速器，其功率-面积效率（PAE）达到了6.6 TOPS/W/mm²。