Neural decoders for quantum error correction (QEC) rely on neural networks to classify syndromes extracted from error correction codes and find appropriate recovery operators to protect logical information against errors. Despite the good performance of neural decoders, important practical requirements remain to be achieved, such as minimizing the decoding time to meet typical rates of syndrome generation in repeated error correction schemes, and ensuring the scalability of the decoding approach as the code distance increases. Designing a dedicated integrated circuit to perform the decoding task in co-integration with a quantum processor appears necessary to reach these decoding time and scalability requirements, as routing signals in and out of a cryogenic environment to be processed externally leads to unnecessary delays and an eventual wiring bottleneck. In this work, we report the design and performance analysis of a neural decoder inference accelerator based on an in-memory computing (IMC) architecture, where crossbar arrays of resistive memory devices are employed to both store the synaptic weights of the decoder neural network and perform analog matrix-vector multiplications during inference. In proof-of-concept numerical experiments supported by experimental measurements, we investigate the impact of TiO$_\textrm{x}$-based memristive devices' non-idealities on decoding accuracy. Hardware-aware training methods are developed to mitigate the loss in accuracy, allowing the memristive neural decoders to achieve a pseudo-threshold of $9.23\times 10^{-4}$ for the distance-three surface code, whereas the equivalent digital neural decoder achieves a pseudo-threshold of $1.01\times 10^{-3}$. This work provides a pathway to scalable, fast, and low-power cryogenic IMC hardware for integrated QEC.

翻译：量子纠错（QEC）神经解码器依赖神经网络对从纠错码中提取的综合征进行分类，并寻找合适的恢复算子以保护逻辑信息免受错误影响。尽管神经解码器性能优异，但仍需满足重要的实际需求，例如最小化解码时间以适应重复纠错方案中综合征生成的典型速率，以及确保解码方法随码距增加的可扩展性。设计专用集成电路，使其与量子处理器协同集成以执行解码任务，对于满足解码时间和可扩展性要求至关重要——因为将信号路由进出低温环境进行外部处理会导致不必要的延迟，并最终形成布线瓶颈。本文报告了一种基于内存计算（IMC）架构的神经解码器推理加速器的设计与性能分析，其中采用阻变存储器交叉阵列来存储解码器神经网络的突触权重，并在推理过程中执行模拟矩阵-向量乘法。在由实验测量支持的概念验证数值实验中，我们研究了基于TiO$_mathrm{x}$的忆阻器件非理想性对解码精度的影响。通过开发硬件感知训练方法以缓解精度损失，忆阻神经解码器对距离为三的表面码实现了$9.23\times 10^{-4}$的伪阈值，而等效数字神经解码器的伪阈值为$1.01\times 10^{-3}$。本工作为集成量子纠错提供了可扩展、快速且低功耗的低温IMC硬件实现路径。