Time-domain nonvolatile in-memory computing (TD-nvIMC) offers a promising pathway to reduce data movement and improve energy efficiency by encoding computation in delay rather than voltage or current. This work presents a fully integrated and reconfigurable TD-nvIMC macro, fabricated in 28 nm CMOS, that combines a ferroelectric FET (FeFET)-based content-addressable memory array, a cascaded delay element chain, and a time-to-digital converter. The architecture supports binary multiply-and-accumulate (MAC) operations using XOR- and AND-based matching, as well as in-memory Boolean logic and arithmetic functions. Sub-nanosecond MAC resolution is achieved through experimentally demonstrated 550 ps delay steps, representing a 2000$\times$ improvement over prior FeFET TD-nvIMC work, enabled by multilevel-state calibration with $\leq$ 100 ps resolution. Write-disturb resilience is ensured via isolated triple-well bulks. The proposed macro achieves a measured throughput of 222.2 MOPS/cell and energy efficiency of 1887 TOPS/W at 0.85 V, establishing a viable path toward scalable, energy-efficient TD-nvIMC accelerators.

翻译：时域非易失性内存计算（TD-nvIMC）通过将计算编码在延迟而非电压或电流中，为减少数据移动和提高能效提供了一条前景广阔的途径。本文提出了一种完全集成且可重构的TD-nvIMC宏单元，该宏单元采用28纳米CMOS工艺制造，集成了基于铁电场效应晶体管（FeFET）的内容可寻址存储器阵列、级联延迟元件链以及时间数字转换器。该架构支持使用基于XOR和AND匹配的二进制乘累加（MAC）运算，以及内存内布尔逻辑和算术函数。通过实验验证的550 ps延迟步长实现了亚纳秒级MAC分辨率，这相较于先前的FeFET TD-nvIMC工作提升了2000倍，这得益于分辨率≤100 ps的多级状态校准技术。通过隔离的三阱体结构确保了抗写入干扰能力。所提出的宏单元在0.85 V电压下实现了实测222.2 MOPS/单元的吞吐量和1887 TOPS/W的能效，为构建可扩展、高能效的TD-nvIMC加速器确立了一条可行的技术路径。