Transformers' compute-intensive operations pose enormous challenges for their deployment in resource-constrained EdgeAI / tinyML devices. As an established neural network compression technique, quantization reduces the hardware computational and memory resources. In particular, fixed-point quantization is desirable to ease the computations using lightweight blocks, like adders and multipliers, of the underlying hardware. However, deploying fully-quantized Transformers on existing general-purpose hardware, generic AI accelerators, or specialized architectures for Transformers with floating-point units might be infeasible and/or inefficient. Towards this, we propose SwiftTron, an efficient specialized hardware accelerator designed for Quantized Transformers. SwiftTron supports the execution of different types of Transformers' operations (like Attention, Softmax, GELU, and Layer Normalization) and accounts for diverse scaling factors to perform correct computations. We synthesize the complete SwiftTron architecture in a $65$ nm CMOS technology with the ASIC design flow. Our Accelerator executes the RoBERTa-base model in 1.83 ns, while consuming 33.64 mW power, and occupying an area of 273 mm^2. To ease the reproducibility, the RTL of our SwiftTron architecture is released at https://github.com/albertomarchisio/SwiftTron.

翻译：Transformer的高计算密集度特性对其在资源受限的EdgeAI/tinyML设备中的部署构成了巨大挑战。作为成熟的神经网络压缩技术，量化可降低硬件计算与存储资源需求。其中，定点量化特别适用于通过加法器、乘法器等轻量级模块简化底层硬件计算。然而，在现有通用硬件、通用AI加速器或采用浮点单元的专用Transformer架构上部署全量化Transformer可能面临不可行或低效的问题。为此，我们提出SwiftTron——专为量化Transformer设计的高效专用硬件加速器。该加速器支持执行多种Transformer操作（如注意力机制、Softmax、GELU与层标准化），并兼容多种缩放因子以确保精确计算。我们采用65纳米CMOS工艺，通过ASIC设计流程完成了SwiftTron完整架构的综合。本加速器执行RoBERTa-base模型仅需1.83纳秒，功耗33.64毫瓦，占用面积273平方毫米。为便于结果复现，SwiftTron架构的RTL代码已开源至https://github.com/albertomarchisio/SwiftTron。