The Internet of Things infrastructure connects a massive number of edge devices with an increasing demand for intelligent sensing and inferencing capability. Such data-sensitive functions necessitate energy-efficient and programmable implementations of Error Correction Codes (ECC) and decoders. The algorithmic flow of ECCs with concurrent accumulation and comparison types of operations are innately exploitable by neuromorphic architectures for energy efficient execution -- an area that is relatively unexplored outside of machine learning applications. For the first time, we propose a methodology to map the hard-decision class of decoder algorithms on a neuromorphic architecture. We present the implementation of the Gallager B (GaB) decoding algorithm on a TrueNorth-inspired architecture that is emulated on the Xilinx Zynq ZCU102 MPSoC. Over this reference implementation, we propose architectural modifications at the neuron block level that result in a reduction of energy consumption by 31% with a negligible increase in resource usage while achieving the same error correction performance.

翻译：物联网基础设施连接大量边缘设备，对智能感知与推理能力的需求日益增长。这类数据敏感功能要求纠错码（ECC）及其解码器具备高能效且可编程的实现方案。纠错码算法流程中涉及的并发累加与比较操作，天然适用于神经形态架构的高能效执行——这一领域在机器学习应用之外尚未得到充分探索。我们首次提出一种将硬判决类解码器算法映射至神经形态架构的方法论。本文展示了在受TrueNorth启发的架构上实现的Gallager B（GaB）解码算法，该架构通过Xilinx Zynq ZCU102 MPSoC进行仿真。基于此参考实现，我们在神经元模块层级提出架构改进，可在资源占用几乎不变且保持相同纠错性能的前提下，使能耗降低31%。