Layer assignment is critical for global routing of VLSI circuits. It converts 2D routing paths into 3D routing solutions by determining the proper metal layer for each routing segments to minimize congestion and via count. As different layers have different unit resistance and capacitance, layer assignment also has significant impacts to timing and power. With growing design complexity, it becomes increasingly challenging to simultaneously optimize timing, power, and congestion efficiently. Existing studies are mostly limited to a subset of objectives. In this paper, we propose a GPU-accelerated performance-driven layer assignment framework, GAP-LA, for holistic optimization the aforementioned objectives. Experimental results demonstrate that we can achieve 0.3%-9.9% better worst negative slack (WNS) and 2.0%-5.4% better total negative slack (TNS) while maintaining power and congestion with competitive runtime compared with ISPD 2025 contest winners, especially on designs with up to 12 millions of nets.

翻译：层分配对于超大规模集成电路（VLSI）的全局布线至关重要。它通过为每个布线线段确定合适的金属层，将二维布线路径转换为三维布线解决方案，以最小化拥塞和通孔数量。由于不同层具有不同的单位电阻和电容，层分配对时序和功耗也具有显著影响。随着设计复杂度的增加，如何高效地同时优化时序、功耗和拥塞变得越来越具有挑战性。现有研究大多局限于优化部分目标。本文提出了一种GPU加速的性能驱动层分配框架GAP-LA，用于对上述目标进行整体优化。实验结果表明，与ISPD 2025竞赛优胜方案相比，我们能够在保持功耗和拥塞水平的同时，获得0.3%-9.9%更优的最差负时序裕量（WNS）和2.0%-5.4%更优的总负时序裕量（TNS），且运行时间具有竞争力，尤其是在布线网数量高达1200万的设计上。