Compute Express Link (CXL) switch allows memory extension via PCIe physical layer to address increasing demand for larger memory capacities in data centers. However, CXL attached memory introduces 170ns to 400ns memory latency. This becomes a significant performance bottleneck for applications that host data in persistent memory as all updates, after traversing the CXL switch, must reach persistent domain to ensure crash consistent updates.We make a case for persistent CXL switch to persist updates as soon as they reach the switch and hence significantly reduce latency of persisting data. To enable this, we presented a system independent persistent buffer (PB) design that ensures data persistency at CXL switch. Our PB design provides 12\% speedup, on average, over volatile CXL switch. Our \textit{read forwarding} optimization improves speedup to 15\%.

翻译：计算快速链路（CXL）交换机通过PCIe物理层实现内存扩展，以应对数据中心对更大内存容量日益增长的需求。然而，CXL附加内存会引入170纳秒至400纳秒的内存访问延迟。对于将数据存储在持久内存中的应用程序而言，这成为一个显著的性能瓶颈，因为所有更新在穿越CXL交换机后都必须抵达持久化域以确保崩溃一致性。我们提出采用持久化CXL交换机，使数据更新在抵达交换机时即刻持久化，从而显著降低数据持久化的延迟。为实现这一目标，我们提出了一种系统无关的持久化缓冲区（PB）设计，确保在CXL交换机层面实现数据持久性。我们的PB设计相比易失性CXL交换机平均带来12%的性能加速。通过\textit{读取转发}优化，性能加速可进一步提升至15%。