Recent hardware acceleration advances have enabled powerful specialized accelerators for finite element computations, spiking neural network inference, and sparse tensor operations. However, existing approaches face fundamental limitations: (1) finite element methods lack comprehensive rounding error analysis for reduced-precision implementations and use fixed precision assignment strategies that cannot adapt to varying numerical conditioning; (2) spiking neural network accelerators cannot handle non-spike operations and suffer from bit-width escalation as network depth increases; and (3) FPGA tensor accelerators optimize only for dense computations while requiring manual configuration for each sparsity pattern. To address these challenges, we introduce \textbf{Memory-Guided Unified Hardware Accelerator for Mixed-Precision Scientific Computing}, a novel framework that integrates three enhanced modules with memory-guided adaptation for efficient mixed-workload processing on unified platforms. Our approach employs memory-guided precision selection to overcome fixed precision limitations, integrates experience-driven bit-width management and dynamic parallelism adaptation for enhanced spiking neural network acceleration, and introduces curriculum learning for automatic sparsity pattern discovery. Extensive experiments on FEniCS, COMSOL, ANSYS benchmarks, MNIST, CIFAR-10, CIFAR-100, DVS-Gesture datasets, and COCO 2017 demonstrate 2.8\% improvement in numerical accuracy, 47\% throughput increase, 34\% energy reduction, and 45-65\% throughput improvement compared to specialized accelerators. Our work enables unified processing of finite element methods, spiking neural networks, and sparse computations on a single platform while eliminating data transfer overhead between separate units.

翻译：近期硬件加速技术的进步已催生出针对有限元计算、脉冲神经网络推理及稀疏张量运算的强大专用加速器。然而，现有方法面临根本性局限：(1) 有限元方法缺乏针对低精度实现的全面舍入误差分析，且采用固定的精度分配策略，无法适应变化的数值条件；(2) 脉冲神经网络加速器无法处理非脉冲操作，且随着网络深度增加面临位宽膨胀问题；(3) FPGA张量加速器仅针对稠密计算进行优化，且需为每种稀疏模式进行手动配置。为应对这些挑战，我们提出了**面向混合精度科学计算的记忆引导统一硬件加速器**，这是一种新颖的框架，集成了三个增强模块，并采用记忆引导自适应机制，以在统一平台上实现高效的混合工作负载处理。我们的方法采用记忆引导精度选择以克服固定精度限制，集成经验驱动的位宽管理与动态并行度自适应以增强脉冲神经网络加速，并引入课程学习以实现自动稀疏模式发现。在FEniCS、COMSOL、ANSYS基准测试、MNIST、CIFAR-10、CIFAR-100、DVS-Gesture数据集以及COCO 2017上进行的大量实验表明，与专用加速器相比，我们的方法在数值精度上提升了2.8%，吞吐量提高了47%，能耗降低了34%，吞吐量提升了45-65%。我们的工作实现了在单一平台上对有限元方法、脉冲神经网络及稀疏计算的统一处理，同时消除了不同独立单元间的数据传输开销。