Quantum error correction (QEC) codes can tolerate hardware errors by encoding fault-tolerant logical qubits using redundant physical qubits and detecting errors using parity checks. Leakage errors occur in quantum systems when a qubit leaves its computational basis and enters higher energy states. These errors severely limit the performance of QEC due to two reasons. First, they lead to erroneous parity checks that obfuscate the accurate detection of errors. Second, the leakage spreads to other qubits and creates a pathway for more errors over time. Prior works tolerate leakage errors by using leakage reduction circuits (LRCs) that modify the parity check circuitry of QEC codes. Unfortunately, naively using LRCs always throughout a program is sub-optimal because LRCs incur additional two-qubit operations that (1) facilitate leakage transport, and (2) serve as new sources of errors. Ideally, LRCs should only be used if leakage occurs, so that errors from both leakage as well as additional LRC operations are simultaneously minimized. However, identifying leakage errors in real-time is challenging. To enable the robust and efficient usage of LRCs, we propose ERASER that speculates the subset of qubits that may have leaked and only uses LRCs for those qubits. Our studies show that the majority of leakage errors typically impact the parity checks. We leverage this insight to identify the leaked qubits by analyzing the patterns in the failed parity checks. We propose ERASER+M that enhances ERASER by detecting leakage more accurately using qubit measurement protocols that can classify qubits into $|0\rangle, |1\rangle$ and $|L\rangle$ states. ERASER and ERASER+M improve the logical error rate by up to $4.3\times$ and $23\times$ respectively compared to always using LRC.

翻译：量子纠错码通过使用冗余物理量子比特编码容错逻辑量子比特，并利用奇偶校验检测错误，从而容忍硬件错误。量子系统中的泄漏错误发生于量子比特脱离计算基态并进入更高能级状态时。此类错误因以下两个原因严重限制量子纠错性能：首先，它们会导致错误的奇偶校验，混淆对错误的准确检测；其次，泄漏会扩散至其他量子比特，并随时间推移为更多错误创造传播路径。先前工作通过使用修改量子纠错码奇偶校验电路的泄漏抑制电路来容忍泄漏错误。然而，在程序运行过程中始终幼稚地使用泄漏抑制电路并非最优方案，因为泄漏抑制电路会引入额外的双量子比特操作，这些操作不仅会促进泄漏传输，还会成为新的错误源。理想的方案是仅在泄漏发生时使用泄漏抑制电路，从而同时最小化来自泄漏和额外泄漏抑制电路操作造成的错误。但实时识别泄漏错误极具挑战性。为实现泄漏抑制电路的鲁棒高效使用，我们提出ERASER方法，该方法推测可能发生泄漏的量子比特子集，并仅对这些量子比特使用泄漏抑制电路。研究表明，大多数泄漏错误主要影响奇偶校验。我们利用这一洞察，通过分析失败奇偶校验的模式来识别泄漏量子比特。进一步提出ERASER+M方法，通过采用能将量子比特分类为$|0\rangle$、$|1\rangle$和$|L\rangle$态的量子比特测量协议，更准确地检测泄漏。相比于始终使用泄漏抑制电路，ERASER和ERASER+M分别将逻辑错误率提升了最高$4.3\times$和$23\times$。