We explore the use of Large Language Models (LLMs) to generate high-quality Register-Transfer Level (RTL) code with minimal human interference. The traditional RTL design workflow requires human experts to manually write high-quality RTL code, which is time-consuming and error-prone. With the help of emerging LLMs, developers can describe their requirements to LLMs which then generate corresponding code in Python, C, Java, and more. Adopting LLMs to generate RTL design in hardware description languages is not trivial, given the complex nature of hardware design and the generated design has to meet the timing and physical constraints. We propose VeriAssist, an LLM-powered programming assistant for Verilog RTL design workflow. VeriAssist takes RTL design descriptions as input and generates high-quality RTL code with corresponding test benches. VeriAssist enables the LLM to self-correct and self-verify the generated code by adopting an automatic prompting system and integrating RTL simulator in the code generation loop. To generate an RTL design, VeriAssist first generates the initial RTL code and corresponding test benches, followed by a self-verification step that walks through the code with test cases to reason the code behavior at different time steps, and finally it self-corrects the code by reading the compilation and simulation results and generating final RTL code that fixes errors in compilation and simulation. This design fully leverages the LLMs' capabilities on multi-turn interaction and chain-of-thought reasoning to improve the quality of the generated code. We evaluate VeriAssist with various benchmark suites and find it significantly improves both syntax and functionality correctness over existing LLM implementations, thus minimizing human intervention and making RTL design more accessible to novice designers.

翻译：本文探索利用大语言模型（LLMs）以最小人工干预生成高质量寄存器传输级（RTL）代码的方法。传统RTL设计流程需要领域专家手动编写高质量RTL代码，这一过程既耗时又容易出错。借助新兴的LLMs技术，开发者可向模型描述需求，由模型生成相应的Python、C、Java等语言代码。然而，由于硬件设计的复杂性及生成设计需满足时序与物理约束，将LLMs应用于硬件描述语言的RTL设计生成并非易事。我们提出VeriAssist——一个基于LLM的Verilog RTL设计流程编程助手。VeriAssist以RTL设计描述为输入，生成高质量的RTL代码及对应测试平台。该系统通过采用自动提示机制并将RTL仿真器集成至代码生成循环，使LLM能够对生成代码进行自校正与自验证。在生成RTL设计时，VeriAssist首先生成初始RTL代码与对应测试平台，随后执行自验证步骤：通过测试用例逐步遍历代码以推理不同时间步的代码行为，最后通过读取编译与仿真结果进行自校正，生成能够修复编译与仿真错误的最终RTL代码。该设计充分利用了LLMs在多轮交互和思维链推理方面的能力，从而提升生成代码的质量。我们在多种基准测试集上评估VeriAssist，发现其相较于现有LLM实现方案能显著提升语法正确性与功能正确性，从而最大限度减少人工干预，降低RTL设计对新手工程师的门槛。