The challenges associated with effectively programming FPGAs have been a major blocker in popularising reconfigurable architectures for HPC workloads. However new compiler technologies, such as MLIR, are providing new capabilities which potentially deliver the ability to extract domain specific information and drive automatic structuring of codes for FPGAs. In this paper we explore domain specific optimisations for stencils, a fundamental access pattern in scientific computing, to obtain high performance on FPGAs via automated code structuring. We propose Stencil-HMLS, a multi-layered approach to automatic optimisation of stencil codes and introduce the HLS dialect, which brings FPGA programming into the MLIR ecosystem. Using the PSyclone Fortran DSL, we demonstrate an improvement of 14-100$\times$ with respect to the next best performant state-of-the-art tool. Furthermore, our approach is 14 to 92 times more energy efficient than the next most energy efficient approach.

翻译：有效编程FPGA所面临的挑战一直是阻碍可重构架构在HPC工作负载中普及的主要障碍。然而，诸如MLIR等新型编译器技术正提供新能力，有望提取领域特定信息并驱动FPGA代码的自动结构化。本文探索了模板计算（科学计算中的一种基本访问模式）的领域特定优化方法，通过自动化代码结构在FPGA上实现高性能。我们提出了Stencil-HMLS——一种用于模板代码自动优化的多层次方法，并引入了HLS方言，将FPGA编程纳入MLIR生态系统。利用PSyclone Fortran DSL，我们展示了相较于次优性能的最先进工具，性能提升达14-100倍。此外，我们的方法在能效上比次优能效方法高出14至92倍。