Recent advancements in large language models (LLMs) boasting billions of parameters have generated a significant demand for efficient deployment in inference workloads. The majority of existing approaches rely on temporal architectures that reuse hardware units for different network layers and operators. However, these methods often encounter challenges in achieving low latency due to considerable memory access overhead. This paper investigates the feasibility and potential of model-specific spatial acceleration for LLM inference on FPGAs. Our approach involves the specialization of distinct hardware units for specific operators or layers, facilitating direct communication between them through a dataflow architecture while minimizing off-chip memory accesses. We introduce a comprehensive analytical model for estimating the performance of a spatial LLM accelerator, taking into account the on-chip compute and memory resources available on an FPGA. Through our analysis, we can determine the scenarios in which FPGA-based spatial acceleration can outperform its GPU-based counterpart. To enable more productive implementations of an LLM model on FPGAs, we further provide a library of high-level synthesis (HLS) kernels that are composable and reusable. This library will be made available as open-source. To validate the effectiveness of both our analytical model and HLS library, we have implemented BERT and GPT2 on an AMD Alveo U280 FPGA device. Experimental results demonstrate our approach can achieve up to 16.1x speedup when compared to previous FPGA-based accelerators for the BERT model. For GPT generative inference, we attain a 2.2x speedup compared to DFX, an FPGA overlay, in the prefill stage, while achieving a 1.9x speedup and a 5.7x improvement in energy efficiency compared to the NVIDIA A100 GPU in the decode stage.

翻译：近期，拥有数十亿参数的大语言模型（LLMs）的发展对高效推理部署产生了巨大需求。现有方法大多采用时序架构，通过复用硬件单元处理不同网络层与算子，然而这类方法常因显著的内存访问开销而难以实现低延迟。本文研究了在FPGA上为LLM推理定制模型专属空间加速器的可行性与潜力。我们的方法为特定算子或层专门设计硬件单元，通过数据流架构实现单元间的直接通信，同时尽量减少片外内存访问。我们提出了一个综合分析模型，该模型基于FPGA可用的片上计算与内存资源评估空间LLM加速器的性能。通过该分析，我们能够判定基于FPGA的空间加速超越GPU方案的适用场景。为提升FPGA上LLM模型实现的效率，我们进一步提供了可组合、可复用的高层次综合（HLS）内核库（将以开源形式发布）。为验证分析模型与HLS库的有效性，我们在AMD Alveo U280 FPGA上实现了BERT与GPT2模型。实验结果表明，与先前基于FPGA的BERT加速器相比，本方法可实现最高16.1倍的加速比；在GPT生成式推理中，预填充阶段相比FPGA覆盖层DFX获得了2.2倍加速，解码阶段相比NVIDIA A100 GPU实现了1.9倍加速与5.7倍的能效提升。