Modern Out-of-Order (OoO) CPUs are complex systems with many components interleaved in non-trivial ways. Pinpointing performance bottlenecks and understanding the underlying causes of program performance issues are critical tasks to fully exploit the performance offered by hardware resources. Current performance debugging approaches rely either on measuring resource utilization, in order to estimate which parts of a CPU induce performance limitations, or on code-based analysis deriving bottleneck information from capacity/throughput models. These approaches are limited by instrumental and methodological precision, present portability constraints across different microarchitectures, and often offer factual information about resource constraints, but not causal hints about how to solve them. This paper presents a novel performance debugging and analysis tool that implements a resource-centric CPU model driven by dynamic binary instrumentation that is capable of detecting complex bottlenecks caused by an interplay of hardware and software factors. Bottlenecks are detected through sensitivity-based analysis, a sort of model parameterization that uses differential analysis to reveal constrained resources. It also implements a new technique we developed that we call causality analysis, that propagates constraints to pinpoint how each instruction contribute to the overall execution time. To evaluate our analysis tool, we considered the set of high-performance computing kernels obtained by applying a wide range of transformations from the Polybench benchmark suite and measured the precision on a few Intel CPU and Arm micro-architectures. We also took one of the benchmarks (correlation) as an illustrative example to illustrate how our tool's bottleneck analysis can be used to optimize a code.

翻译：现代乱序执行（OoO）CPU 是由众多组件以复杂方式交织而成的复杂系统。准确定位性能瓶颈并理解程序性能问题的根本原因，是充分利用硬件资源所提供性能的关键任务。当前的性能调试方法要么依赖于测量资源利用率，以估计 CPU 的哪些部分导致了性能限制；要么依赖于基于代码的分析，从容量/吞吐量模型中推导瓶颈信息。这些方法受限于仪器和方法的精度，存在跨不同微架构的可移植性约束，并且通常仅提供关于资源约束的事实信息，而非如何解决这些约束的因果性提示。本文提出了一种新颖的性能调试与分析工具，该工具实现了一个以资源为中心的 CPU 模型，该模型由动态二进制插桩驱动，能够检测由硬件和软件因素相互作用引起的复杂瓶颈。瓶颈通过基于敏感性的分析进行检测，这是一种利用微分分析来揭示受限资源的模型参数化方法。该工具还实现了一种我们开发的新技术，我们称之为因果关系分析，它通过传播约束来精确定位每条指令对总执行时间的贡献。为了评估我们的分析工具，我们考虑了通过应用 Polybench 基准测试套件中广泛变换而获得的高性能计算内核集合，并在几款 Intel CPU 和 Arm 微架构上测量了其精度。我们还选取其中一个基准测试（correlation）作为示例，以说明如何利用我们工具的瓶颈分析来优化代码。