Recently, nature-inspired computing approaches have gained significant attention for solving difficult optimization problems, particularly through Ising machines for NP-complete applications. Existing Ising accelerators range from quantum and optical annealers to CMOS-based von-Neumann and in-memory architectures. However, many prior designs are specialized accelerators limited to specific problem classes, rely on ADC/DAC circuits, and suffer from reliability challenges due to process-variation-sensitive embedded memory technologies. This paper presents SACHI, an all-digital Ising architecture implemented by repurposing the L1 cache of a CPU using SRAM-based processing-in-memory techniques. SACHI eliminates the need for ADCs/DACs, improves reliability compared to prior approaches such as BRIM, and enables Ising acceleration with minimal hardware overhead integrated into the CPU pipeline. The paper also provides detailed architectural analysis and pseudo-code for the proposed algorithms. The key contributions of SACHI are: (i) tight integration of the accelerator with the CPU pipeline, (ii) reuse of existing cache hardware for acceleration, (iii) higher parallelism enabled through reuse-aware computation, and (iv) improved performance and energy efficiency for large-scale, high-precision optimization problems using novel compute and mapping strategies. Compared to BRIM, SACHI achieves 300x performance improvement and 80x energy reduction across applications including asset allocation, molecular dynamics, image segmentation, and traveling salesman problems. Additionally, reuse factors up to 4000x are observed for several workloads. This work demonstrates that reliable and efficient all-digital Ising acceleration can be achieved using commodity SRAM structures tightly integrated with general-purpose processors.

翻译：近年来，受自然启发的计算方法在解决困难优化问题方面引起了广泛关注，尤其是通过伊辛机解决NP完全应用问题。现有的伊辛加速器涵盖从量子退火器和光学退火器到基于CMOS的冯·诺依曼架构和存内架构。然而，许多早期设计属于局限于特定问题类别的专用加速器，依赖模数/数模转换电路（ADC/DAC），并且因对工艺变化敏感的嵌入式存储技术而面临可靠性挑战。本文提出SACHI——一种通过使用基于SRAM的存内计算技术重新利用CPU一级缓存实现的全数字伊辛架构。SACHI消除了对ADC/DAC的需求，相比BRIM等先前方法提升了可靠性，并通过最小化硬件开销集成到CPU流水线中实现伊辛加速。本文还提供了所提算法的详细架构分析和伪代码。SACHI的关键贡献包括：(i) 加速器与CPU流水线的紧密集成，(ii) 复用现有缓存硬件实现加速，(iii) 通过复用感知计算实现更高的并行度，以及 (iv) 利用新颖计算与映射策略在大规模高精度优化问题上实现更高的性能和能效。相比BRIM，SACHI在资产配置、分子动力学、图像分割和旅行商问题等应用中实现了300倍的性能提升和80倍的能耗降低。此外，针对多个负载观察到高达4000倍的复用因子。这项工作表明，使用与通用处理器紧密集成的商用SRAM结构可以实现可靠且高效的全数字伊辛加速。