The increasing demand for heterogeneous functionality in the automotive industry and the evolution of chip manufacturing processes have led to the transition from federated to integrated critical real-time embedded systems (CRTESs). This leads to higher integration challenges of conventional timing predictability techniques due to access contention on shared resources, which can be resolved by providing system-level observability and controllability in hardware. We focus on the interconnect as a shared resource and propose AXI-REALM, a lightweight, modular, and technology-independent real-time extension to industry-standard AXI4 interconnects, available open-source. AXI-REALM uses a credit-based mechanism to distribute and control the bandwidth in a multi-subordinate system on periodic time windows, proactively prevents denial of service from malicious actors in the system, and tracks each manager's access and interference statistics for optimal budget and period selection. We provide detailed performance and implementation cost assessment in a 12nm node and an end-to-end functional case study implementing AXI-REALM into an open-source Linux-capable RISC-V SoC. In a system with a general-purpose core and a hardware accelerator's DMA engine causing interference on the interconnect, AXI-REALM achieves fair bandwidth distribution among managers, allowing the core to recover 68.2 % of its performance compared to the case without contention. Moreover, near-ideal performance (above 95 %) can be achieved by distributing the available bandwidth in favor of the core, improving the worst-case memory access latency from 264 to below eight cycles. Our approach minimizes buffering compared to other solutions and introduces only 2.45 % area overhead compared to the original SoC.

翻译：汽车行业对异构功能需求的日益增长以及芯片制造工艺的演进，促使关键实时嵌入式系统从联邦式向集成式架构转变。这导致共享资源访问竞争加剧了传统时序可预测性技术的集成挑战，可通过硬件级系统可观测性与可控制性加以解决。本文聚焦作为共享资源的互连架构，提出AXI-REALM——一种面向工业标准AXI4互连的轻量、模块化且技术无关的实时扩展方案，并以开源形式发布。该机制采用基于信用量的方法，在周期性时间窗口内对多从属系统进行带宽分配与控制，主动防御恶意实体引发的拒绝服务攻击，并追踪每个管理器的访问与干扰统计信息以实现最优预算和周期选择。我们基于12nm工艺节点进行了详细的性能与实现成本评估，并通过将AXI-REALM集成至开源Linux兼容RISC-V SoC的端到端功能案例研究，验证了其实用性。在通用核心与硬件加速器DMA引擎对互连产生干扰的系统中，AXI-REALM实现了管理器间的公平带宽分配，使核心性能相比无竞争情况恢复68.2%。此外，通过将可用带宽偏向核心分配，可实现接近理想性能（优于95%），并将最坏情况下的访存延迟从264个时钟周期降至8个时钟周期以下。相较于其他解决方案，本方法最大限度减少了数据缓冲需求，且相比原始SoC仅引入2.45%的面积开销。