Chiplet technology enables the integration of an increasing number of transistors on a single accelerator with higher yield in the post-Moore era, addressing the immense computational demands arising from rapid AI advancements. However, it also introduces more expensive packaging costs and costly Die-to-Die (D2D) interfaces, which require more area, consume higher power, and offer lower bandwidth than on-chip interconnects. Maximizing the benefits and minimizing the drawbacks of chiplet technology is crucial for developing large-scale DNN chiplet accelerators, which poses challenges to both architecture and mapping. Despite its importance in the post-Moore era, methods to address these challenges remain scarce.

翻译：芯粒技术在后摩尔时代能够以更高的良率将越来越多的晶体管集成到单个加速器上，从而满足人工智能快速发展带来的巨大计算需求。然而，它也会引入更昂贵的封装成本和昂贵的Die-to-Die（D2D）接口，这些接口与片上互连相比，需要更大的面积、消耗更高的功耗，并提供更低的带宽。最大化芯粒技术的优势并最小化其劣势对于开发大规模DNN芯粒加速器至关重要，这对架构和映射都带来了挑战。尽管该技术在后摩尔时代具有重要性，但应对这些挑战的方法仍然匮乏。