Tydi is an open specification for streaming dataflow designs in digital circuits, allowing designers to express how composite and variable-length data structures are transferred over streams using clear, data-centric types. These data types are extensively used in a many application domains, such as big data and SQL applications. This way, Tydi provides a higher-level method for defining interfaces between components as opposed to existing bit and byte-based interface specifications. In this paper, we introduce an open-source intermediate representation (IR) which allows for the declaration of Tydi's types. The IR enables creating and connecting components with Tydi Streams as interfaces, called Streamlets. It also lets backends for synthesis and simulation retain high-level information, such as documentation. Types and Streamlets can be easily reused between multiple projects, and Tydi's streams and type hierarchy can be used to define interface contracts, which aid collaboration when designing a larger system. The IR codifies the rules and properties established in the Tydi specification and serves to complement computation-oriented hardware design tools with a data-centric view on interfaces. To support different backends and targets, the IR is focused on expressing interfaces, and complements behavior described by hardware description languages and other IRs. Additionally, a testing syntax for the verification of inputs and outputs against abstract streams of data, and for substituting interdependent components, is presented which allows for the specification of behavior. To demonstrate this IR, we have created a grammar, parser, and query system, and paired these with a backend targeting VHDL.

翻译：Tydi是一个用于数字电路中流式数据流设计的开放规范，允许设计者通过清晰、以数据为中心的类型，表达复合和可变长度数据结构如何在流上传输。这些数据类型广泛应用于大数据和SQL应用等众多领域。通过这种方式，Tydi提供了一种比现有基于比特和字节的接口规范更高级的方法来定义组件之间的接口。本文介绍了一种开源中间表示（IR），它支持声明Tydi的类型。该中间表示能够创建和连接以Tydi流为接口的组件（称为Streamlets），并允许用于综合和仿真的后端保留高级信息（如文档）。类型和Streamlets可以在多个项目之间轻松复用，Tydi的流和类型层级可用于定义接口契约，从而在大型系统设计时促进协作。该中间表示将Tydi规范中确立的规则和属性编码化，并通过以数据为中心的接口视角来补充面向计算的硬件设计工具。为支持不同的后端和目标，该中间表示专注于表达接口，并补充了由硬件描述语言及其他中间表示描述的行为。此外，本文还介绍了一种针对抽象数据流的输入输出验证以及可替代组件的测试语法，该语法允许对行为进行规范。为演示该中间表示，我们构建了一个语法、解析器和查询系统，并将其与面向VHDL的后端配对使用。