This study aims to ensure consistency in accuracy throughout the entire design flow in the implementation of edge AI hardware for few-shot learning, by implementing fixed-point data processing in the pre-training and evaluation phases. Specifically, the quantization module, called Brevitas, is applied to implement fixed-point data processing, which allows for arbitrary specification of the bit widths for the integer and fractional parts. Two methods of fixed-point data quantization, quantization-aware training (QAT) and post-training quantization (PTQ), are utilized in Brevitas. With Tensil, which is used in the current design flow, the bit widths of the integer and fractional parts need to be 8 bits each or 16 bits each when implemented in hardware, but performance validation has shown that accuracy comparable to floating-point operations can be maintained even with 6 bits or 5 bits each, indicating potential for further reduction in computational resources. These results clearly contribute to the creation of a versatile design and evaluation environment for edge AI hardware for few-shot learning.

翻译：本研究旨在通过在前训练与评估阶段实现定点数据处理，确保少样本学习边缘AI硬件实现过程中整个设计流程的精度一致性。具体而言，应用名为Brevitas的量化模块实现定点数据处理，该模块允许对整数部分与小数部分的位宽进行任意指定。Brevitas中采用了两种定点数据量化方法：量化感知训练（QAT）与训练后量化（PTQ）。在当前设计流程使用的Tensil框架中，硬件实现时整数部分与小数部分的位宽需各自为8位或16位，但性能验证表明，即使采用各自6位或5位的配置，仍能保持与浮点运算相当的精度，这显示出进一步减少计算资源的潜力。这些成果显著促进了少样本学习边缘AI硬件通用化设计与评估环境的构建。