In this study, we propose an implementation methodology of real-time few-shot learning on tiny FPGA SoCs such as the PYNQ-Z1 board with arbitrary fixed-point bit-widths. Tensil-based conventional design environments limited hardware implementations to fixed-point bit-widths of 16 or 32 bits. To address this, we adopt the FINN framework, enabling implementations with arbitrary bit-widths. Several customizations and minor adjustments are made, including: 1.Optimization of Transpose nodes to resolve data format mismatches, 2.Addition of handling for converting the final reduce mean operation to Global Average Pooling (GAP). These adjustments allow us to reduce the bit-width while maintaining the same accuracy as the conventional realization, and achieve approximately twice the throughput in evaluations using CIFAR-10 dataset.

翻译：本研究提出了一种在PYNQ-Z1等微型FPGA SoC上实现任意定点比特宽度实时少样本学习的实施方法。基于Tensil的传统设计环境将硬件实现限制在16或32位定点比特宽度。为解决此问题，我们采用FINN框架，实现了任意比特宽度的部署。我们进行了若干定制化与微调，包括：1.优化Transpose节点以解决数据格式不匹配问题；2.增加将最终reduce mean运算转换为全局平均池化（GAP）的处理机制。这些调整使我们能在保持与传统实现相同精度的同时降低比特宽度，并在CIFAR-10数据集评估中实现约两倍的吞吐量。