Offloading stateful network functions to multi-threaded SoC SmartNICs promises significant performance and cost benefits. However, realizing this potential is hindered by two fundamental challenges. First, without performance guidance, developers are forced into a slow, manual trial-and-error cycle of deploying and testing to find a feasible resource allocation. Second, sustaining performance under changing traffic requires adapting state residency and handling overload within memory layouts fixed at compile time. This paper introduces Vela, a framework that addresses both challenges through a model-driven, compile-time/runtime co-design. Its core is a predictive compiler that replaces the manual tuning loop with fast, automated analysis, using a novel, state-centric analytical model to estimate the throughput ceiling of any given resource allocation plan. This is complemented by a lightweight runtime that dynamically manages cache contents within the compiled memory layout and mitigates overload. We implement and evaluate Vela on Netronome Agilio and NVIDIA BlueField 3 SmartNICs across four NFs. Vela reduces host CPU or on-board Arm core usage by 62.9%-91.9% relative to the best baseline achieving the same throughput. For the NATLB workload, vela also improves throughput by 15.2%-120.8% over the best baseline at the same host/Arm core count.

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