Selective hardening is widely employed to improve the reliability of FPGA based soft processors while limiting the overhead of full redundancy. However, existing approaches primarily rely on architectural criticality or functional fault analysis, overlooking the impact of routing dependent timing sensitivity on processor robustness. This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs. Building on recent advances in in situ timing observability, the proposed approach quantifies the statistical timing sensitivity of pipeline components under controlled routing perturbations and uses this information to guide hardening decisions. Experimental results on a RISCV processor implemented on a commercial FPGA platform show that components exhibiting higher timing fragility also demonstrate increased vulnerability to routing induced delay effects. Leveraging this correlation, the proposed selective hardening strategy achieves robustness comparable to full hardening while significantly reducing area and timing overhead. These results demonstrate that timing fragility provides a practical and effective metric for reliability aware design optimization in FPGA based processor architectures.

翻译：选择性硬化被广泛用于提高基于FPGA的软处理器的可靠性，同时限制完全冗余的开销。然而，现有方法主要依赖于架构关键性或功能故障分析，忽视了布线相关的时序敏感性对处理器鲁棒性的影响。本文针对SRAM型FPGA上实现的RISCV软处理器，提出了一种时序脆弱性感知的选择性硬化方法。基于原位时序可观测性的最新进展，所提方法量化了流水线组件在受控布线扰动下的统计时序敏感性，并利用该信息指导硬化决策。在商用FPGA平台上实现的RISCV处理器实验结果表明，表现出较高时序脆弱性的组件对布线引起的延迟效应也显示出更高的脆弱性。利用这种相关性，所提出的选择性硬化策略实现了与完全硬化相当的鲁棒性，同时显著减少了面积和时序开销。这些结果表明，时序脆弱性为基于FPGA的处理器架构中可靠性感知的设计优化提供了一个实用且有效的度量指标。