In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft countermeasures is hard to achieve. Using embedded configurable logic allows designers to completely hide the functionality of selected design portions from parties that do not have access to the configuration string (bitstream). However, the design space of redacted solutions is huge, with trade-offs between the portions selected for redaction and the configuration of the configurable embedded logic. We propose ARIANNA, a complete flow that aids the designer in all the stages, from selecting the logic to be hidden to tailoring the bespoke fabrics for the configurable logic used to hide it. We present a security evaluation of the considered fabrics and introduce two heuristics for the novel bespoke fabric flow. We evaluate the heuristics against an exhaustive approach. We also evaluate the complete flow using a selection of benchmarks. Results show that using ARIANNA to customize the redaction fabrics yields up to 3.3x lower overheads and 4x higher eFPGA fabric utilization than a one-fits-all fabric as proposed in prior works.

翻译：在现代全球集成电路供应链中，知识产权保护是一项复杂的挑战，难以在IP泄露风险与反窃取措施带来的额外成本之间取得平衡。利用嵌入式可配置逻辑，设计者能够对未获得配置字符串（比特流）的各方完全隐藏选定设计部分的功能。然而，功能隐匿解决方案的设计空间极为庞大，需要在选定隐匿部分与嵌入式可配置逻辑的配置方案之间进行权衡。本文提出ARIANNA——一套完整的设计流程，可辅助设计者完成从待隐匿逻辑选择到用于隐藏逻辑的定制化可配置逻辑架构裁剪的全阶段工作。我们对所考虑的架构进行了安全性评估，并针对新颖的定制化架构流程提出了两种启发式方法。我们通过穷举方法对这两种启发式方法进行了评估，并利用一组基准测试案例对完整流程进行了综合评估。结果表明，相较于先前工作中提出的通用架构，使用ARIANNA定制化隐匿架构可实现最高3.3倍的开销降低和4倍的eFPGA架构利用率提升。