Due to the increasing challenges posed by the relentless rise in the design complexity of integrated circuits, Boolean Satisfiability (SAT) has emerged as a robust alternative to structural APTG techniques. However, the high cost of transforming a circuit testing problem to a Conjunctive Normal Form (CNF) limits the application of SAT in industrial ATPG scenarios, resulting in a loss of test coverage. In Order to address this problem, this paper proposes a conflict-driven structural learning (CDSL) ATPG algorithm firstly, in which the conflict-driven heuristic methods in modern SAT solver are implemented on the logic cone of fault propagation and activation directly. The proposed CDSL algorithm is composed of three parts: (1) According to the implication graph, various conflict constraints have been learned to prune search space. (2) Conflict-driven implication and justification have been applied to increase decision accuracy and solving efficiency. (3) A conflict-based diagnosis method is further proposed in the case of low coverage debug, leading to making the aborted faults testable by relaxing or modifying some constraints on primary inputs. Extensive experimental results on industrial circuits demonstrate the effectiveness and efficiency of the proposed CDSL algorithm. It is shown that compared with the SAT-based ATPG, the proposed CDSL can on average decrease $25.6\%$ aborted faults with $94.51\%$ less run time. With a two-stage computational flow, it has shown that the proposed CDSL can lead to $46.37\%$ less aborted faults than a one-stage structural algorithm, further with the $3.19\%$ improvement on fault coverage. In addition, the conflict diagnosis can lead to $8.89\%$ less aborted faults on average, and $0.271\%$ improvement in fault coverage rate.

翻译：随着集成电路设计复杂度的持续提升带来的挑战，布尔可满足性（SAT）已成为结构化ATPG技术的可靠替代方案。然而，将电路测试问题转换为合取范式（CNF）的高昂代价限制了SAT在工业ATPG场景中的应用，导致测试覆盖率损失。为解决该问题，本文首次提出冲突驱动的结构化学习（CDSL）ATPG算法，该算法在现代SAT求解器的冲突驱动启发式方法基础上，直接在故障传播与激活的逻辑锥上实现。所提出的CDSL算法由三部分组成：（1）根据蕴含图学习多种冲突约束以剪枝搜索空间；（2）应用冲突驱动的蕴含与判决策略提升决策精度与求解效率；（3）针对低覆盖率调试场景进一步提出基于冲突的诊断方法，通过放松或修改主输入约束使中止故障可测试。大量工业电路实验验证了所提CDSL算法的有效性与高效性。结果表明，与基于SAT的ATPG相比，所提CDSL平均可减少25.6%的中止故障，同时降低94.51%的运行时间。采用两阶段计算流程后，相较于单阶段结构化算法，CDSL平均减少46.37%的中止故障，并提升3.19%的故障覆盖率。此外，冲突诊断平均可减少8.89%的中止故障，故障覆盖率提升0.271%。